The invention relates to a sigma-delta modulator.
As compared with other types of converters, analog/digital converters with sigma-delta modulators are distinguished by the lower cost of analog circuitry. In the simplest case, namely for a first-order sigma-delta modulator, only one integrator with a differential input, one comparator for single-bit quantization and a reference voltage source for digital/analog conversion are required. High oversampling is then used instead of high resolution, and in a subsequent digital or in other words non-critical noise filter, a low-frequency, high-resolution signal is recovered from the high-frequency, low-resolution signal. The advantage then is that the attainable resolution is determined by the oversampling factor and the noise filtering, while conversely component tolerances do not substantially affect the resolution.
If the modulator order is increased, the resolution rises by 6 dB each time the oversampling factor is doubled. A first-order modulator has a resolution of approximately 9 dB per doubling of the oversampling factor. Therefore that value is approximately 15 dB for a second-order modulator and approximately 21 dB for a third-order modulator.
Second-order sigma-delta modulators are widely used, particularly in the audio field. In the case of a speech band with a bandwidth of 8 kHz and a sampling frequency of 1024 kHz, a resolution of approximately 80 dB or 13 bits is thus attained. By comparison, with a third-order sigma-delta modulator the same resolution is already attained at half the sampling frequency. Since the power consumption varies in proportion with the sampling frequency, power can be saved with a third-order modulator, despite the presence of a further integrator. That is particularly significant for battery-operated equipment.
Third-order sigma-delta modulators with a single feedback loop have stability problems, which is why cascading lower-order stable modulators are currently being done instead. Cascading first-order sigma-delta modulators has the advantage of not requiring scaling to avoid voltage magnification at the integrator outputs. In that kind of cascading, the quantization error of the first first-order sigma-delta modulator is digitally converted by the next sigma-delta modulator and then subtracted from the digital signal of the first sigma-delta modulator by a logical network. The output signal of the thus-formed third order sigma-delta modulator includes a noise component that originates in the first first-order sigma-delta modulator and cannot be fully compensated for.
In that respect, cascading of a second-order sigma-delta modulator and of a following first-order sigma-delta modulator is more favorable. However, the disadvantage of that circuit is that the noise is increased further because of the necessary scaling of the analog part, since the scaling must be rescinded again after the digital part after the quantization.
An article entitled "Third-Order Cascaded Sigma-Delta Modulators", by L. A. Williams and B. A. Wooley, in IEEE Transactions on Circuits and Systems, Vol. 38, No. 5, May 1991, discloses a third-order cascaded sigma-delta modulator circuit, including a second-order modulator and a following first-order modulator. Due to suitable scaling, that circuit does not have the disadvantage mentioned above. The known circuit includes a known integrator to which the difference, weighted with a first coefficient, between an input signal and a first reference signal is applied, and a second integrator to which the difference, weighted by a second coefficient, between the output signal of the first integrator and the first reference signal is applied. A first quantizer, to which the output signal of the second integrator is delivered, and a first digital/analog converter, which converts the output signal of the first quantizer into the first reference signal, are also provided. Moreover, the output signal of the second integrator, weighted by a third coefficient, is subtracted from the first reference signal, weighted by a fourth coefficient, and the resultant difference is then multiplied by a fifth coefficient. A second reference signal is subtracted from that product. The resultant difference is weighted by a sixth coefficient and delivered to a third integrator. The output of the third integrator is applied to a second quantizer, which in turn is followed by a second digital/analog converter for generating the second reference signal. Finally, each of the two quantizers are followed by respective digital filters, having output signals which are subtracted from one another and produce the output signal of the third-order sigma-delta modulator.
However, a disadvantage of such a sigma-delta modulator is that in constructing it with circuitry for coupling the second-order modulator to the first-order modulator, either one additional analog subtractor or an analog subtractor with three inputs is needed.
It is accordingly an object of the invention to provide a cascaded sigma-delta modulator with a higher-order modulator and a following first-order modulator, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a sigma-delta modulator, comprising a first integrator receiving a difference between an input signal being weighted by a first coefficient, and a first reference signal being weighted by a second coefficient, the first integrator supplying an output signal; a second integrator receiving a difference between the output signal of the first integrator being weighted by a third coefficient, and the first reference signal being weighted by a fourth coefficient, the second integrator supplying an output signal; a first quantizer receiving the output signal of the second integrator being weighted by a fifth coefficient, the first quantizer supplying an output signal; a first digital/analog converter receiving and converting the output signal of the first quantizer into the first reference signal; a third integrator receiving a difference between the output signal of the second integrator being weighted by a sixth coefficient, and a second reference signal being weighted by a seventh coefficient, the third integrator supplying an output signal; a second quantizer receiving the output signal of the third integrator being weighted by an eighth coefficient, the second quantizer supplying an output signal; a logic circuit receiving and adding together the output signals of the first and second quantizers and supplying an output signal; a second digital/analog converter receiving and converting the output signal of the logic circuit into the second reference signal; and a first digital filter connected downstream of the first quantizer, and a second digital filter connected downstream of the second quantizer, the digital filters supplying output signals being added together.
In accordance with another feature of the invention, the first digital filter forms a sum of the triply delayed output signal of the first quantizer being weighted by a ninth coefficient, the doubly delayed output signal of the first quantizer being weighted by the doubled, negative, ninth coefficient, and the singly delayed output signal of the first quantizer being weighted by the ninth coefficient+1; and the second digital filter forms a sum of the doubly delayed output signal of the second quantizer being weighted by a tenth coefficient, the doubled, negative, singly delayed output signal of the second quantizer, and the undelayed output signal of the second quantizer.
In accordance with an added feature of the invention, the first coefficient is equal to a reciprocal of a first constant being multiplied by a ratio of maximum quantity values of the input signal to the first reference signal; the second coefficient is equal to the reciprocal of the first constant; the third coefficient is equal to a ratio of the first constant to a second constant; the fourth coefficient is equal to twice a reciprocal of the second constant; the sixth coefficient is equal to a product of the second constant, a reciprocal of a third constant, and a fourth constant; the seventh coefficient is equal to twice the reciprocal of the third constant; the ninth coefficient is equal to twice a reciprocal of the fourth constant, minus 1; the tenth coefficient is equal to the reciprocal of the fourth constant; and the maximum quantity values of the two reference signals are of equal size.
In accordance with a concomitant feature of the invention, there is provided at least one further integrator connected upstream of the first integrator, the at least one further integrator receiving a difference between a respective input signal being weighted with further coefficients, and the first reference signal.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a sigma-delta modulator, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.